The present invention relates to magnetic bubble memory devices and particularly to improvements in the arrangement of the storage and gating functions in a magnetic bubble array.
The conventional major minor and block replicate type of bubble memory chip arrays utilize bubble storage means formed of a selected type of propagate elements arranged in loops with transfer-in and transfer-out and/or replicate gates (ports) located at the ends of each loop. These loops, called storage loops, have bubbles continuously circulating therein in response to an in-plane rotating magnetic field. These loops are normally elongated with the gating function located at the corner turn for the bubble propagating therein. Since this corner turn is a 180 degree turn, the propagate and other functional elements are crowded at this point and, often, the lowest magnetic margins exist because of these crowded conditions. This problem is impacted further as bubble sizes diminish and chip sizes increase.
Stated another way, in a normal bubble memory arrangement having a plurality of storage loops, it is conventional to provide a transfer function at the ends of each of the loops, ie. two ports for each loop. Take first a chip of a fixed size with a given bubble size, as an example, a chip utilizing four micron bubbles in an array of 100 storage loops having a transfer-in port at one end and a replicate port at the other end. If a chip of the same size is now selected to use two microns bubbles, then 200 storage loops would be required and the loop lengths would be twice as many bits long. This now has increased the number of transfer-in ports from 100 to 200 and the replicate port number also increased from 100 to 200. This means that with the two micron bubbles, smaller ports are used requiring thinner metalization but since there are twice as many ports, the transfer line resistances have more than doubled. This increase places a burden on the driving circuitry because the voltage required of the drive control circuits continues to increase beyond the range of low cost readily accessible electronics.
The object of this invention is to provide a means for reducing the transfer impedances in a bubble memory array as bubble sizes diminish and/or chip sizes increase and thus decrease the burden on the driving circuitry therefor.
A second object of this invention is to provide a memory array with a means for transferring and for other functions operable at a lower current in a loop configuration with an accompanying reduction in control conductor thickness and chip yield improvements.
A still further object of this invention is to provide a memory array with greater flexibility in arranging the timing between transfer ports and between other functional elements by selecting the number of propagate elements (steps) between such ports and elements.